EPM5192-1LC vs EPM5192LC-1 Comparison
Detailed side-by-side comparison of EPM5192-1LC by Altera and EPM5192LC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192LC-1
EPM5192LC-1 - 192-Macrocell MAX 5000 CPLD, 5V, 84-LDCC | Altera
EPM5192LC-1 ObsoleteSpecification Comparison
| Parameter | EPM5192-1LC | EPM5192LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.40 | $14.20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD / CPLD |
| Usable Gates | 3,750 | β |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 4 | β |
| User I/O Pins | 64 | β |
| Maximum Operating Frequency | 62.5 MHz | β |
| Propagation Delay (tpd) | [DATA_NEEDED: -1 speed grade tpd in ns] | β |
| Supply Voltage | 5 V | 5 V nominal (4.75 V to 5.25 V) |
| Process Technology | UV EPROM, erasable windowless | β |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | β |
| JTAG Boundary Scan | IEEE 1149.1 compliant | β |
| Package | 64-pin Ceramic J-Lead Chip Carrier (LC) | β |
| Mounting Type | Surface Mount | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS Status | Non-compliant (ceramic windowless package, lead-bearing termination) | Non-compliant (ceramic LDCC with Pb-bearing terminations) |
| Logic Gates | β | 3750 (typical usable) |
| Dedicated Inputs | β | 7 |
| User I/O | β | 64 |
| Number of Pins | β | 84 |
| Package Type | β | LDCC (Leaded Ceramic Chip Carrier), plastic windowless |
| Propagation Delay | β | 25 ns |
| Maximum Clock Frequency | β | 50 MHz |
| Technology | β | CMOS, UV-erasable / OTP EPROM cell |
| Programmable Memory | β | EPROM (one-time or UV-erasable) |
| Speed Grade | β | -1 |