EPM5192AGC-15 vs EPM5192-1LC Comparison
Detailed side-by-side comparison of EPM5192AGC-15 by Altera and EPM5192-1LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AGC-15
EPM5192AGC-15 - 192-Macrocell MAX 5000 EPLD | Altera | 15ns
EPM5192AGC-15 ObsoleteSpecification Comparison
| Parameter | EPM5192AGC-15 | EPM5192-1LC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $27.80 | $19.40 |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Series | MAX 5000 | β |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (typical for 192-macrocell MAX 5000) | β |
| Maximum User I/O Pins | 64 | β |
| Dedicated Inputs | 7 | β |
| Total Inputs | 72 | β |
| Propagation Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | β |
| Supply Voltage (VCC) | 5 V | β |
| Technology | CMOS, UV-erasable EPROM | β |
| Package | Ceramic Pin Grid Array (PGA) | 64-pin Ceramic J-Lead Chip Carrier (LC) |
| Programming Method | UV erase + EPROM program (via Altera programmer) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| RoHS Status | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] | Non-compliant (ceramic windowless package, lead-bearing termination) |
| Lifecycle Status | Obsolete / Last Time Buy (per Altera legacy product list) | β |
| Family | β | MAX 5000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 3,750 |
| Logic Array Blocks (LABs) | β | 4 |
| User I/O Pins | β | 64 |
| Maximum Operating Frequency | β | 62.5 MHz |
| Propagation Delay (tpd) | β | [DATA_NEEDED: -1 speed grade tpd in ns] |
| Supply Voltage | β | 5 V |
| Process Technology | β | UV EPROM, erasable windowless |
| Programmable Interconnect | β | PIA (Programmable Interconnect Array) |
| JTAG Boundary Scan | β | IEEE 1149.1 compliant |
| Mounting Type | β | Surface Mount |