EPM5192AGC vs EPM5192AGC-15 Comparison
Detailed side-by-side comparison of EPM5192AGC by Altera and EPM5192AGC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192AGC | EPM5192AGC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $56.00 | $27.80 |
| Family | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) | β |
| Device Type | UV-Erasable / OTP Complex PLD (EPLD) | β |
| Macrocells | 192 | 192 |
| Logic Density | High-density (per MAX 5000 family definition) | β |
| Architecture | CMOS, sum-of-products with macrocell output logic | β |
| Process Technology | CMOS | β |
| Package | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) | Ceramic Pin Grid Array (PGA) |
| Speed Grade Suffix | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Programmability | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) | β |
| Security Bit | Programmable security bit (per MAX 5000 family) | β |
| Supply Voltage | [DATA_NEEDED: VCC nominal and tolerance] | β |
| Mounting Type | Through-hole (Pin Grid Array) | β |
| RoHS Status | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] |
| Lifecycle | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) | β |
| Programming Support | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers | β |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Series | β | MAX 5000 |
| Logic Array Blocks | β | 16 (typical for 192-macrocell MAX 5000) |
| Maximum User I/O Pins | β | 64 |
| Dedicated Inputs | β | 7 |
| Total Inputs | β | 72 |
| Propagation Delay (tPD) | β | 15 ns (pin-to-pin, -15 speed grade) |
| Supply Voltage (VCC) | β | 5 V |
| Technology | β | CMOS, UV-erasable EPROM |
| Programming Method | β | UV erase + EPROM program (via Altera programmer) |
| Lifecycle Status | β | Obsolete / Last Time Buy (per Altera legacy product list) |