EPM5192AJC-15 vs EPM5192AJC-25 Comparison
Detailed side-by-side comparison of EPM5192AJC-15 by Intel and EPM5192AJC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192AJC-15 | EPM5192AJC-25 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $8.20 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Macrocells | 192 | 192 |
| Logic Capacity | 100% connectivity, sum-of-products PLA architecture | β |
| Pin-to-Pin Delay (tPD) | 15 ns | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | β |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: exact operating temperature range] |
| Package | 84-pin PLCC (J-lead, ceramic, non-windowed) | PLCC-68 (windowed ceramic, AJC) |
| Mounting Type | Surface Mount | Surface Mount |
| Programmability | UV-erasable (windowed variant) / One-Time-Programmable | β |
| Toolchain | MAX+PLUS II | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Pin Count | 84 | 68 |
| User I/O Pins | [DATA_NEEDED: user I/O count] | β |
| Speed Grades Available | -15, -20, -25 (this part: -15) | β |
| Configuration Memory | EPROM (UV-erasable) | β |
| Manufacturer | β | Altera (now Intel PSG) |
| Propagation Delay (tPD) | β | 25 ns |
| Supply Voltage | β | 5 V (typical) |
| Logic Blocks | β | MAX 5000 LABs (Logic Array Blocks) |
| Programmable Pins | β | [DATA_NEEDED: number of user I/O pins] |
| Erasure Method | β | UV-erasable (windowed ceramic package) |
| Programming Technology | β | EPROM (non-volatile) |
| Military Grade | β | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) |