EPM5192AJC-15 vs EPM5192GC1 Comparison

Detailed side-by-side comparison of EPM5192AJC-15 by Intel and EPM5192GC1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5192GC1

EPM5192GC1 - MAX 5000 CPLD 192-Macrocell 62.5MHz 5V | Altera

EPM5192GC1 Obsolete

Specification Comparison

Parameter EPM5192AJC-15 EPM5192GC1
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.85 $24.50
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 192 β€”
Logic Capacity 100% connectivity, sum-of-products PLA architecture β€”
Pin-to-Pin Delay (tPD) 15 ns β€”
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 5 V
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Package 84-pin PLCC (J-lead, ceramic, non-windowed) β€”
Mounting Type Surface Mount Through-hole (PGA)
Programmability UV-erasable (windowed variant) / One-Time-Programmable β€”
Toolchain MAX+PLUS II β€”
RoHS Status [DATA_NEEDED: RoHS compliance] unknown
Pin Count 84 β€”
User I/O Pins [DATA_NEEDED: user I/O count] β€”
Speed Grades Available -15, -20, -25 (this part: -15) β€”
Configuration Memory EPROM (UV-erasable) β€”
Macro Cells β€” 192
Usable Gates β€” 3,750
Maximum Operating Frequency β€” 62.5 MHz
Programming Technology β€” UV-Erasable / OTP EPROM
Package Type β€” Ceramic PGA (Pin Grid Array)
Logic Elements β€” 192 macrocells with AND/OR array
Process Technology β€” EPROM-based CMOS
Propagation Delay β€” [DATA_NEEDED: tpd specification]
Number of Pins β€” [DATA_NEEDED: pin count for GC1 PGA package]
Development Tool β€” Altera MAX+PLUS II

Datasheets & Resources

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