EPM5192AJC84-15 vs EPM5192AJC-15 Comparison
Detailed side-by-side comparison of EPM5192AJC84-15 by Altera and EPM5192AJC-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 ObsoleteSpecification Comparison
| Parameter | EPM5192AJC84-15 | EPM5192AJC-15 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.95 | $9.85 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 15 ns | β |
| Maximum Clock Frequency (fMAX) | 83.3 MHz | β |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable EPROM | β |
| Package | 84-pin PLCC (J84C) windowed ceramic | 84-pin PLCC (J-lead, ceramic, non-windowed) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | 0C to +70C (commercial) |
| Programming Method | UV-erase + EPROM programming (windowed package) | β |
| Logic Blocks | 16 Logic Array Blocks (LABs) | β |
| I/O Pins | [DATA_NEEDED: user I/O count] | β |
| RoHS Status | Non-compliant (contains Pb, ceramic windowed package) | [DATA_NEEDED: RoHS compliance] |
| Process Technology | CMOS EPROM | β |
| Logic Capacity | β | 100% connectivity, sum-of-products PLA architecture |
| Pin-to-Pin Delay (tPD) | β | 15 ns |
| Programmability | β | UV-erasable (windowed variant) / One-Time-Programmable |
| Toolchain | β | MAX+PLUS II |
| Pin Count | β | 84 |
| User I/O Pins | β | [DATA_NEEDED: user I/O count] |
| Speed Grades Available | β | -15, -20, -25 (this part: -15) |
| Configuration Memory | β | EPROM (UV-erasable) |