EPM5192AJC84-15 vs EPM5192ALC84-15 Comparison
Detailed side-by-side comparison of EPM5192AJC84-15 by Altera and EPM5192ALC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 ObsoleteSpecification Comparison
| Parameter | EPM5192AJC84-15 | EPM5192ALC84-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.95 | $13.20 |
| Family | MAX 5000 | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD / UV-Erasable / OTP Complex PLD |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 15 ns | β |
| Maximum Clock Frequency (fMAX) | 83.3 MHz | β |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V (nominal 5 V) |
| Technology | CMOS, UV-erasable EPROM | β |
| Package | 84-pin PLCC (J84C) windowed ceramic | 84-pin PLCC (QCCJ, J-bend ceramic) |
| Mounting Type | Surface Mount | β |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | β |
| Programming Method | UV-erase + EPROM programming (windowed package) | β |
| Logic Blocks | 16 Logic Array Blocks (LABs) | β |
| I/O Pins | [DATA_NEEDED: user I/O count] | β |
| RoHS Status | Non-compliant (contains Pb, ceramic windowed package) | β |
| Process Technology | CMOS EPROM | CMOS (EPROM-based) |
| Device Family | β | MAX 5000 (EPM5192) |
| Dedicated Inputs | β | 7 |
| User I/O Pins | β | 64 |
| Propagation Delay (tPD) | β | 15 ns |
| Propagation Delay (Industry Variant) | β | 25 ns (per MicrochipUSA listing) |
| Programmability | β | UV-erasable window / OTP |
| Operating Temperature Grade | β | Commercial |
| Terminal Form | β | J-BEND |
| Package Code | β | QCCJ |
| Package Shape | β | SQUARE |
| Architecture | β | Programmable Logic Array + Macrocell Registers + PIA interconnect |