EPM5192AJI84-15 vs EPM5192AGC-15 Comparison

Detailed side-by-side comparison of EPM5192AJI84-15 by Altera and EPM5192AGC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192AJI84-15 EPM5192AGC-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $27.80 $27.80
Device Family MAX 5000 EPLD β€”
Product Type UV-Erasable / OTP Complex PLD EPLD (Erasable Programmable Logic Device)
Macrocells 192 192
Logic Array Blocks (LABs) 16 β€”
User I/O Pins 84 β€”
Propagation Delay (tPD) 15 ns 15 ns (pin-to-pin, -15 speed grade)
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) 5 V
Process Technology CMOS EPROM (UV-erasable) β€”
Package Type 84-pin JLCC (J-Leaded Ceramic Chip Carrier) with quartz window β€”
Mounting Type Through-Hole (SMD socket-compatible) β€”
Operating Temperature -40 Β°C to +85 Β°C (Industrial, 'I' suffix) [DATA_NEEDED: operating temperature range]
Programming Method UV erase + EPROM program via standard Altera programmer UV erase + EPROM program (via Altera programmer)
Design Tool Support MAX+PLUS II (legacy); not supported by modern Quartus Prime β€”
RoHS Status unknown [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant]
Lead-Free unknown β€”
Halogen-Free unknown β€”
Functional Equivalent (Plastic OTP) EPM5192AJC84-15 (windowless plastic JLCC, same die) β€”
Series β€” MAX 5000
Logic Array Blocks β€” 16 (typical for 192-macrocell MAX 5000)
Maximum User I/O Pins β€” 64
Dedicated Inputs β€” 7
Total Inputs β€” 72
Technology β€” CMOS, UV-erasable EPROM
Package β€” Ceramic Pin Grid Array (PGA)
Lifecycle Status β€” Obsolete / Last Time Buy (per Altera legacy product list)

Datasheets & Resources

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