EPM5192AJI84-20 vs EPM5192AGC84-20 Comparison
Detailed side-by-side comparison of EPM5192AJI84-20 by Altera and EPM5192AGC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AJI84-20
EPM5192AJI84-20 - 192-Macrocell UV EPLD, 33ns | Altera MAX 5000
EPM5192AJI84-20 ObsoleteAltera
EPM5192AGC84-20
EPM5192AGC84-20 - 192-Macrocell MAX 5000 UV PLD | Altera | 84-CPGA
EPM5192AGC84-20 ObsoleteSpecification Comparison
| Parameter | EPM5192AJI84-20 | EPM5192AGC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.95 | $41.20 |
| Device Family | MAX 5000 (EPM5192) | β |
| Logic Cells / Macrocells | 192 macrocells | β |
| Device Type | UV-Erasable / OTP Complex PLD | β |
| Propagation Delay (tPD) | 33 ns | β |
| Maximum Frequency (fCNT) | 66.7 MHz | β |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | β |
| Process Technology | CMOS | CMOS |
| Operating Temperature Grade | Industrial | Commercial |
| Package Code | WQCCJ (JEDEC) | WPGA |
| Package Type | 84-pin J-bend Ceramic Chip Carrier (PLCC-84, JI) | β |
| Mounting Type | Surface Mount | Through-Hole (Pin Grid Array socket) |
| Terminal Form | J-Bend | β |
| Number of Terminals | 84 | β |
| Programmability | UV-erasable window + OTP | β |
| Pin Count | 84 | β |
| Lifecycle Status | Obsolete (legacy Altera MAX 5000) | β |
| RoHS Status | [DATA_NEEDED: RoHS status of EPM5192AJI84-20] | [DATA_NEEDED: RoHS compliance] |
| Product Type | β | Complex Programmable Logic Device (CPLD) |
| Family | β | MAX 5000 |
| Macrocells | β | 192 |
| User I/O Pins | β | 64 |
| Dedicated Inputs | β | 7 |
| Logic Gates (typical) | β | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | β | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Speed Grade | β | -20 |
| Package | β | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Erasure Method | β | UV-Erasable (with OTP window) |
| Supply Voltage | β | [DATA_NEEDED: VCC range] |
| I/O Standard | β | 5V CMOS / TTL compatible |