EPM5192ALC84-15 vs EPM5192AJC84-15 Comparison

Detailed side-by-side comparison of EPM5192ALC84-15 by Altera and EPM5192AJC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192ALC84-15 EPM5192AJC84-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $13.20 $18.95
Device Family MAX 5000 (EPM5192) β€”
Device Type CPLD / UV-Erasable / OTP Complex PLD EPLD (Erasable Programmable Logic Device)
Macrocells 192 192
Dedicated Inputs 7 β€”
User I/O Pins 64 β€”
Propagation Delay (tPD) 15 ns β€”
Propagation Delay (Industry Variant) 25 ns (per MicrochipUSA listing) β€”
Supply Voltage (VCC) 4.75 V to 5.25 V (nominal 5 V) 5 V (single supply)
Process Technology CMOS (EPROM-based) CMOS EPROM
Programmability UV-erasable window / OTP β€”
Package 84-pin PLCC (QCCJ, J-bend ceramic) 84-pin PLCC (J84C) windowed ceramic
Operating Temperature Grade Commercial β€”
Terminal Form J-BEND β€”
Package Code QCCJ β€”
Package Shape SQUARE β€”
Architecture Programmable Logic Array + Macrocell Registers + PIA interconnect β€”
Family β€” MAX 5000
Propagation Delay (tpd) β€” 15 ns
Maximum Clock Frequency (fMAX) β€” 83.3 MHz
Technology β€” CMOS, UV-erasable EPROM
Mounting Type β€” Surface Mount
Operating Temperature β€” [DATA_NEEDED: commercial/industrial/military grade]
Programming Method β€” UV-erase + EPROM programming (windowed package)
Logic Blocks β€” 16 Logic Array Blocks (LABs)
I/O Pins β€” [DATA_NEEDED: user I/O count]
RoHS Status β€” Non-compliant (contains Pb, ceramic windowed package)

Datasheets & Resources

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