EPM5192AQC-2 vs EPM5192C-2 Comparison
Detailed side-by-side comparison of EPM5192AQC-2 by Altera and EPM5192C-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192AQC-2 | EPM5192C-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.50 | $13.20 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | Complex Programmable Logic Device (CPLD) |
| Series | MAX 5000 (EPM5192) | β |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | β |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | β |
| Maximum Clock Frequency | [DATA_NEEDED: max fMAX for -2 grade] | β |
| Process Technology | CMOS | CMOS |
| Switch Matrix | UV-Erasable / OTP (windowless on AQC package) | β |
| Package | 100-pin PQFP (R-PQFP-G100) | β |
| Lead Pitch | 0.635 mm | β |
| Terminal Form | Gull-wing | β |
| Operating Temperature | [DATA_NEEDED: commercial / industrial / military grade] | β |
| Mounting Type | Surface Mount | β |
| Programming Interface | JTAG (IEEE 1149.1) boundary scan | JTAG / Altera MAX+ programming |
| RoHS Status | [DATA_NEEDED: confirmed compliance status] | unknown |
| Family | β | MAX 5000 |
| Logic Array Blocks (LABs) | β | 12 |
| External Clock Inputs | β | 1 |
| Propagation Delay (PIA, typical) | β | 45 ns |
| Maximum Operating Frequency | β | 50 MHz |
| Configuration Memory | β | EEPROM (non-volatile) |
| Programmable Interconnect | β | Programmable Interconnect Array (PIA) |
| Speed Grade | β | -2 |
| Lead-Free | β | unknown |