EPM5192AQC-2 vs EPM5192QC-1 Comparison
Detailed side-by-side comparison of EPM5192AQC-2 by Altera and EPM5192QC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192AQC-2 | EPM5192QC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.50 | $9.95 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | OTP PLD (One-Time-Programmable) |
| Series | MAX 5000 (EPM5192) | β |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | β |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | 40 ns |
| Maximum Clock Frequency | [DATA_NEEDED: max fMAX for -2 grade] | β |
| Process Technology | CMOS | CMOS |
| Switch Matrix | UV-Erasable / OTP (windowless on AQC package) | β |
| Package | 100-pin PQFP (R-PQFP-G100) | PQFP-100 (R-PQFP-G100) |
| Lead Pitch | 0.635 mm | 0.650 mm |
| Terminal Form | Gull-wing | Gull-wing |
| Operating Temperature | [DATA_NEEDED: commercial / industrial / military grade] | β |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) boundary scan | β |
| RoHS Status | [DATA_NEEDED: confirmed compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Family | β | MAX 5000 |
| Logic Array Blocks (LABs) | β | 12 |
| Maximum Clock Frequency (fMAX) | β | 50 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| External Clock Pins | β | 1 (shared clock) |
| Configuration Memory | β | EPROM (OTP, windowless) |