EPM5192AQM100-15 vs EPM5192AQM100-20 Comparison

Detailed side-by-side comparison of EPM5192AQM100-15 by Altera and EPM5192AQM100-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192AQM100-15 EPM5192AQM100-20
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $16.20 $8.20
Family MAX 5000 β€”
Device Type EPLD (Erasable PLD) β€”
Logic Array Blocks (LABs) 12 β€”
Interconnect Architecture Product Term Sharing (PIA) β€”
User I/O Pins 64 β€”
Dedicated Inputs 7 7
Total Inputs 72 β€”
Pin-to-Pin Delay (tPD) 25 ns β€”
Speed Grade -15 (15 ns macrocell delay) β€”
Package PQFP-100 (R-PQFP-G100) 100-pin PQFP (JESD-30 code R-PQFP-G100)
Process Technology CMOS CMOS EPROM-based
Programming Technology EPROM (UV-erasable) β€”
Supply Voltage 5 V (typical, single supply) [DATA_NEEDED: VCC range from datasheet]
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: verified from manufacturer product page]
Operating Temperature [DATA_NEEDED: operating temperature range] β€”
Device Family β€” MAX 5000 (EPLD / classic CPLD)
Logic Elements β€” 192 macrocells across 12 Logic Array Blocks (LABs)
Number of LABs β€” 12
User I/O Lines β€” 64
Pin-to-Pin Propagation Delay (tPD) β€” 33 ns
Maximum Clock Frequency (fMAX) β€” 66.7 MHz
Configuration Memory β€” On-chip EPROM (non-volatile, one-time programmable in this package)
Boundary-Scan Test β€” JTAG / IEEE 1149.1 compatible
External Clock Input β€” Yes (global clock pin)
Operating Temperature Grade β€” [DATA_NEEDED: explicit temperature grade from datasheet]

Datasheets & Resources

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