EPM5192GC-1 vs EPM5192GM Comparison
Detailed side-by-side comparison of EPM5192GC-1 by Altera and EPM5192GM by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192GC-1 | EPM5192GM |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.85 | $58.00 |
| Family | MAX 5000 (Classic) | β |
| Logic Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 192 | β |
| Usable Gates | 3,750 | 3,750 |
| Logic Array Blocks (LABs) | 12 | β |
| Dedicated Inputs | 7 | β |
| User I/O Pins | 64 | β |
| Maximum Propagation Delay (tPD) | 40 ns | β |
| Maximum Frequency (fMAX) | 62.5 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Process Technology | CMOS, UV-erasable / OTP | β |
| Package | 100-pin Ceramic PGA (GC) | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| Mounting Type | Through-Hole (PGA) | Through-Hole (PGA) |
| Configuration Method | UV-Erase / One-Time Programmable | β |
| Interconnect | Peripheral Interconnect Array (PIA) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: commercial/industrial/military grade] |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (contains lead in ceramic PGA) |
| Product Family | β | MAX 5000 |
| Device Type | β | UV Erasable Programmable Logic Device (PLD) |
| Technology | β | CMOS |
| Number of Macrocells | β | 192 |
| Pin-to-Pin Delay (tPD) | β | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | β | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | β | 55 ns |
| Erasure Method | β | UV (windowed ceramic package) |
| Supply Voltage | β | [DATA_NEEDED: typical VCC range] |
| Maximum User I/O | β | [DATA_NEEDED: exact I/O count for CPGA-84] |
| Process Node | β | [DATA_NEEDED: CMOS process geometry] |
| Programming Interface | β | JTAG-compatible (per MAX 5000 family) |