EPM5192GC-2 vs EPM5192C-2 Comparison
Detailed side-by-side comparison of EPM5192GC-2 by Altera and EPM5192C-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192GC-2 | EPM5192C-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $92.00 | $13.20 |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (LABs of 16 macrocells each) | β |
| Usable I/O Pins | [DATA_NEEDED: exact user I/O count for PGA package] | β |
| Propagation Delay (tPD) | 12 ns typical (-2 grade) | β |
| Counter Frequency | 100 MHz minimum | β |
| Supply Voltage (VCC) | 5 V nominal | β |
| Technology | CMOS EPROM | β |
| Programmable Technology | UV-erasable / one-time programmable | β |
| Programming Toolchain | Altera MAX+PLUS II | β |
| Package Type | Pin Grid Array (PGA), ceramic | β |
| Operating Temperature | Commercial (0C to +70C) | β |
| Speed Grade | -2 | -2 |
| RoHS Status | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) | unknown |
| Mounting Type | Through-hole (PGA socket) | β |
| Device Type | β | Complex Programmable Logic Device (CPLD) |
| User I/O Pins | β | 64 |
| Logic Array Blocks (LABs) | β | 12 |
| Dedicated Inputs | β | 7 |
| External Clock Inputs | β | 1 |
| Propagation Delay (PIA, typical) | β | 45 ns |
| Maximum Operating Frequency | β | 50 MHz |
| Process Technology | β | CMOS |
| Configuration Memory | β | EEPROM (non-volatile) |
| Programmable Interconnect | β | Programmable Interconnect Array (PIA) |
| Programming Interface | β | JTAG / Altera MAX+ programming |
| Lead-Free | β | unknown |