EPM5192GI-1 vs EPM5192LI-1 Comparison

Detailed side-by-side comparison of EPM5192GI-1 by Altera and EPM5192LI-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192GI-1 EPM5192LI-1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $165.00 $16.40
Family MAX 5000 MAX 5000
Device Type Complex Programmable Logic Device (CPLD) EPLD (UV-Erasable/OTP Complex PLD)
Architecture PAL-type, UV-erasable CMOS EEPROM/EPROM-based, non-volatile, instant-on
Macrocells 192 192
User I/O Pins 64 [DATA_NEEDED: user I/O count for JLCC variant]
Dedicated Inputs 7 β€”
Logic Array Blocks (LABs) 12 β€”
Propagation Delay (tPD) 25 ns [DATA_NEEDED: tPD in ns at -1 grade]
Maximum Clock Frequency (fMAX) 62.5 MHz β€”
Supply Voltage (VCC) 5.0 V β€”
Operating Temperature -40C to +85C (Industrial) [DATA_NEEDED: industrial vs military range]
Package 84-pin PGA (Pin Grid Array), windowed ceramic β€”
Configuration Memory UV-EPROM (windowed ceramic PGA) β€”
Process Technology CMOS CMOS EPROM, UV-erasable
RoHS Status unknown (legacy UV-windowed package) [DATA_NEEDED: RoHS status of ceramic LI variant]
Usable Gates β€” 3,750
Maximum Toggle Frequency β€” 40 MHz
Supply Voltage β€” 5 V
Package Type β€” JLCC (windowed, ceramic, UV-erasable)
Speed Grade β€” -1
Pin Count β€” [DATA_NEEDED: pin count of LI package]
Mounting Type β€” Surface Mount (JLCC with J-leads)
MSL Level β€” [DATA_NEEDED: MSL level]
Lead Free β€” [DATA_NEEDED: lead-free]
Programmable Interconnect β€” Programmable Interconnect Array (PIA)

Datasheets & Resources

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