EPM5192GI84 vs EPM5192GC84-1 Comparison
Detailed side-by-side comparison of EPM5192GI84 by Altera and EPM5192GC84-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192GI84 | EPM5192GC84-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.80 | $14.20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | β |
| Macrocells | 192 | 192 |
| Logic Array Blocks | [DATA_NEEDED: number of LABs] | β |
| Package | 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) | 84-pin PGA (Pin Grid Array), WPGA code |
| Package Code | WPGA | β |
| Operating Voltage (VCC) | 5 V (typical) | β |
| I/O Logic Compatibility | TTL | β |
| Temperature Grade | Industrial | Commercial |
| Programmable Flip-Flop Modes | D, T, JK, SR | β |
| Programmability | UV-erasable (windowed) / OTP | β |
| Programming File Format | JEDEC map via MAX+PLUS II / A+PLUS | β |
| Propagation Delay | [DATA_NEEDED: tPD in ns] | β |
| Max User I/O Pins | [DATA_NEEDED: usable I/O count for this package] | β |
| Operating Temperature Range | -40 C to +85 C (industrial) | β |
| Mounting Type | Through-Hole (PGA socket or PCB pin/peg) | Through-hole (PGA socket) |
| RoHS Status | [DATA_NEEDED: most legacy PGA parts are non-RoHS] | Compliant (per third-party distributor listing) |
| Lead-Free | [DATA_NEEDED: legacy part, likely contains lead] | β |
| Number of Terminals | 84 | β |
| Terminal Form | PIN/PEG | β |
| Package Shape | SQUARE | β |
| Product Type | β | UV-Erasable/OTP Complex PLD (CPLD) |
| Technology | β | CMOS (EPROM-cell based) |
| Propagation Delay (tPD) | β | 40 ns (speed grade -1) |
| Maximum Clock Frequency | β | 50 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Dedicated Inputs | β | 7 |
| User I/O Pins | β | 64 |
| Total Inputs / Outputs | β | 72 inputs / 64 outputs |
| Architecture | β | Shared input/clock and shared product terms |
| Programming Method | β | UV erasure (quartz window) + EPROM programmer |
| Logic Element Type | β | Macrocells with AND/OR array |