EPM5192GM883B-2 vs EPM5192JC-2 Comparison
Detailed side-by-side comparison of EPM5192GM883B-2 by Altera and EPM5192JC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192GM883B-2 | EPM5192JC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $142.00 | $22.50 |
| Family | MAX 5000 | β |
| Device Type | CPLD (Complex Programmable Logic Device), UV-erasable | β |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | 45 ns |
| Maximum Internal Clock Frequency | 33.3 MHz | β |
| Supply Voltage (VCC, nominal) | 5 V | β |
| Technology | 5 V CMOS | β |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| Package | 84-pin Ceramic Pin Grid Array (CPGA), code S-CPGA-P84 | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Package Outline | 28.45 mm square (approx.) | β |
| Military Screening | MIL-STD-883 (per '883' suffix) | β |
| Mounting Type | Through-hole PGA socket | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | β |
| RoHS Status | non_compliant (ceramic CPGA with MIL-STD-883 screening) | [DATA_NEEDED: RoHS compliance] |
| JEDEC Package Code | S-CPGA-P84 | β |
| Device Family | β | MAX 5000 |
| Product Type | β | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | β | 12 |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| External Clock Inputs | β | 1 |
| Maximum Clock Frequency | β | 40 MHz |
| Process Technology | β | CMOS |
| Number of Terminals | β | 84 |
| Programming Method | β | UV-erase / EPROM |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |