EPM5192JC-1N vs EPM5192JC-2 Comparison
Detailed side-by-side comparison of EPM5192JC-1N by Altera and EPM5192JC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JC-1N | EPM5192JC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.85 | $22.50 |
| Family | MAX 5000 | β |
| Device Type | CPLD - Complex Programmable Logic Device | β |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Usable Gates | 3750 | β |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| External Clock Inputs (GCLK) | 1 | β |
| Propagation Delay (tPD) | 40 ns | 45 ns |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Technology | CMOS EPROM (UV-erasable) | β |
| Package | 84-pin Ceramic Quad Flat Pack (CQFP) | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| JEDEC Package Code | S-CQCC-J84 | β |
| Operating Temperature | [DATA_NEEDED: industrial/commercial temperature range] | β |
| Programming Interface | JTAG / Altera ByteBlaster | β |
| Device Family | β | MAX 5000 |
| Product Type | β | UV-erasable Programmable Logic Device (PLD) |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| External Clock Inputs | β | 1 |
| Maximum Clock Frequency | β | 40 MHz |
| Process Technology | β | CMOS |
| Mounting Type | β | Surface Mount |
| Number of Terminals | β | 84 |
| Programming Method | β | UV-erase / EPROM |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |
| RoHS Status | β | [DATA_NEEDED: RoHS compliance] |