EPM5192JC-2 vs EPM5192JI-2 Comparison
Detailed side-by-side comparison of EPM5192JC-2 by Altera and EPM5192JI-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JC-2 | EPM5192JI-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $22.50 | $9.95 |
| Device Family | MAX 5000 | β |
| Product Type | UV-erasable Programmable Logic Device (PLD) | β |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | β |
| Interconnect | Programmable Interconnect Array (PIA) | β |
| User I/O Pins | 64 | β |
| Dedicated Inputs | 7 | 12 |
| External Clock Inputs | 1 | β |
| Propagation Delay (tPD) | 45 ns | β |
| Maximum Clock Frequency | 40 MHz | β |
| Process Technology | CMOS | CMOS EPROM |
| Package | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) | JLCC-68 (J-Lead Ceramic) |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Terminals | 84 | β |
| Programming Method | UV-erase / EPROM | β |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Non-compliant (ceramic JLCC, contains lead) |
| Family | β | MAX 5000 |
| Device Type | β | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | β | 5000 |
| Flip-Flops | β | 192 |
| Speed Grade | β | -2 |
| Operating Temperature | β | 0C to +70C (commercial) |
| Programming Technology | β | UV-Erasable EPROM |
| Architecture | β | Sum-of-products with Programmable Interconnect Array (PIA) |
| Supply Voltage | β | 5 V (typical) |
| Lifecycle Status | β | Obsolete (legacy Altera MAX 5000 family) |