EPM5192JC-ES vs EPM5192JC Comparison

Detailed side-by-side comparison of EPM5192JC-ES by Intel and EPM5192JC by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192JC-ES EPM5192JC
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $16.45 $16.40
Device Family MAX 5000 β€”
Device Type CPLD (EPLD) β€”
Macrocells 192 192
Logic Array Blocks (LABs) 12 12
Interconnect Programmable Interconnect Array (PIA) β€”
Configuration Memory EPROM (UV-erasable, one-time programmable for JC-ES) β€”
Package 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) 68-pin PLCC (JC) windowed ceramic
Mounting Type Surface Mount Surface Mount
Technology CMOS β€”
Programming Altera MAX+PLUS II or compatible programmer β€”
Operating Temperature [DATA_NEEDED: operating temperature range for ES grade] [DATA_NEEDED: commercial / industrial / military grade]
Supply Voltage [DATA_NEEDED: VCC nominal] [DATA_NEEDED: VCC nominal]
User I/O Pins [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] β€”
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: original Altera marking not RoHS]
Lead-Free [DATA_NEEDED: lead-free status] β€”
MSL Level [DATA_NEEDED: MSL rating] β€”
Note Datasheet source: Altera MAX 5000 family document, 52 pages β€”
Product Type β€” CPLD (Complex Programmable Logic Device)
Series β€” EPM5192 (Classic / MAX-class)
Interconnect Architecture β€” Programmable Interconnect Array (PIA)
Process Technology β€” CMOS EPROM (UV-erasable)
Programming Method β€” UV-erase + EPROM programmer
Non-Volatile Configuration β€” Yes (EPROM cell array)
Logic Family β€” Classic CPLD (EPM5xxx series)
Propagation Delay β€” [DATA_NEEDED: tpd spec by speed grade]

Datasheets & Resources

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