EPM5192JC-ES vs EPM5192JC-1 Comparison

Detailed side-by-side comparison of EPM5192JC-ES by Intel and EPM5192JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192JC-ES EPM5192JC-1
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $16.45 $22.40
Device Family MAX 5000 β€”
Device Type CPLD (EPLD) CPLD - Complex Programmable Logic Device
Macrocells 192 192
Logic Array Blocks (LABs) 12 β€”
Interconnect Programmable Interconnect Array (PIA) β€”
Configuration Memory EPROM (UV-erasable, one-time programmable for JC-ES) UV-EPROM (erasable under UV lamp)
Package 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) β€”
Mounting Type Surface Mount β€”
Technology CMOS CMOS, UV-Erasable / OTP
Programming Altera MAX+PLUS II or compatible programmer β€”
Operating Temperature [DATA_NEEDED: operating temperature range for ES grade] 0 C to +70 C (commercial)
Supply Voltage [DATA_NEEDED: VCC nominal] β€”
User I/O Pins [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] 84
RoHS Status [DATA_NEEDED: RoHS compliance] β€”
Lead-Free [DATA_NEEDED: lead-free status] β€”
MSL Level [DATA_NEEDED: MSL rating] β€”
Note Datasheet source: Altera MAX 5000 family document, 52 pages β€”
Family β€” MAX 5000
Usable Gates β€” 3750
Propagation Delay (tPD) β€” 40 ns (speed grade -1)
Maximum Internal Frequency (fMAX) β€” 62.5 MHz
Supply Voltage (VCC) β€” 4.75 V to 5.25 V
Package Type β€” 84-pin Ceramic Quad Flat Pack (CQFP), windowed
JEDEC Package Code β€” S-CQCC-J84
Programming Interface β€” Altera MAX programming interface (parallel, pre-JTAG for this family)
Process β€” CMOS EPROM
I/O Standard β€” TTL/CMOS 5 V compatible

Datasheets & Resources

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