EPM5192JC-ES vs EPM5192JC2 Comparison
Detailed side-by-side comparison of EPM5192JC-ES by Intel and EPM5192JC2 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JC-ES | EPM5192JC2 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.45 | $15.90 |
| Device Family | MAX 5000 | β |
| Device Type | CPLD (EPLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | β |
| Package | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | PLCC-68 (JC) |
| Mounting Type | Surface Mount | Surface Mount (socketable PLCC) |
| Technology | CMOS | β |
| Programming | Altera MAX+PLUS II or compatible programmer | Altera Master Programmer / ByteBlaster via JTAG-style interface |
| Operating Temperature | [DATA_NEEDED: operating temperature range for ES grade] | β |
| Supply Voltage | [DATA_NEEDED: VCC nominal] | β |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | β |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | β |
| Family | β | MAX 5000 |
| Usable Gates (equivalent) | β | 6000 |
| Maximum User I/O | β | 64 |
| Dedicated Inputs | β | 7 |
| External Clock Inputs | β | 1 (with shared input/clock capability) |
| Maximum Clock Frequency | β | 50 MHz |
| Propagation Delay (tPD) | β | 45 ns (speed grade -2) |
| Process Technology | β | CMOS, UV-erasable |