EPM5192JC-ES vs EPM5192JC68 Comparison

Detailed side-by-side comparison of EPM5192JC-ES by Intel and EPM5192JC68 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192JC-ES EPM5192JC68
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $16.45 $15.85
Device Family MAX 5000 MAX 5000
Device Type CPLD (EPLD) β€”
Macrocells 192 β€”
Logic Array Blocks (LABs) 12 β€”
Interconnect Programmable Interconnect Array (PIA) β€”
Configuration Memory EPROM (UV-erasable, one-time programmable for JC-ES) UV-Erasable EPROM
Package 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) β€”
Mounting Type Surface Mount Surface Mount (PLCC socket compatible)
Technology CMOS β€”
Programming Altera MAX+PLUS II or compatible programmer β€”
Operating Temperature [DATA_NEEDED: operating temperature range for ES grade] 0C to 70C (commercial, JC suffix)
Supply Voltage [DATA_NEEDED: VCC nominal] [DATA_NEEDED: VCC]
User I/O Pins [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] 76
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED: lead-free status] β€”
MSL Level [DATA_NEEDED: MSL rating] β€”
Note Datasheet source: Altera MAX 5000 family document, 52 pages β€”
Product Type β€” EPLD (Erasable Programmable Logic Device)
Logic Elements / Macrocells β€” 192 macrocells
Number of Pins β€” 68
Package Type β€” PLCC-68 (J-Lead)
Pin-to-Pin Delay (tPD) β€” [DATA_NEEDED: tPD]
Maximum Frequency (fMAX) β€” [DATA_NEEDED: fMAX]
Programmable Interconnect β€” Programmable Logic Array + Macrocells
Dedicated Inputs β€” 12
Clock Pins β€” 4 dedicated
Programming Tool β€” MAX+PLUS II (legacy)

Datasheets & Resources

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