EPM5192JC2 vs EPM5192JC1 Comparison

Detailed side-by-side comparison of EPM5192JC2 by Intel and EPM5192JC1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192JC2 EPM5192JC1
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $15.90 $48.30
Family MAX 5000 MAX 5000 (MAX 5xxx CPLD)
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 192 β€”
Logic Array Blocks (LABs) 12 β€”
Usable Gates (equivalent) 6000 β€”
Maximum User I/O 64 β€”
Dedicated Inputs 7 β€”
External Clock Inputs 1 (with shared input/clock capability) β€”
Maximum Clock Frequency 50 MHz β€”
Propagation Delay (tPD) 45 ns (speed grade -2) β€”
Process Technology CMOS, UV-erasable 0.5 Β΅m CMOS, UV-erasable EPROM
Interconnect Programmable Interconnect Array (PIA) β€”
Package PLCC-68 (JC) [DATA_NEEDED: exact package from datasheet]
Mounting Type Surface Mount (socketable PLCC) [DATA_NEEDED: surface mount or through-hole]
Programming Altera Master Programmer / ByteBlaster via JTAG-style interface β€”
Manufacturer β€” Intel (formerly Altera Corporation)
Macro Cells β€” 192
Usable Gates β€” 3750
Maximum Operating Frequency β€” 62.5 MHz
Supply Voltage (VCC) β€” 5 V (nominal)
Propagation Delay (typ) β€” [DATA_NEEDED: propagation delay in ns]
I/O Pins β€” [DATA_NEEDED: I/O pin count]
Operating Temperature β€” [DATA_NEEDED: operating temp range]
Programming Interface β€” JTAG-compatible (Altera MAX 5xxx)
Logic Blocks (LABs) β€” 24 (8 macrocells per LAB)
RoHS Status β€” unknown
AEC-Q100 β€” not_applicable
Lifecycle β€” Obsolete - last-time-buy stock only at franchised distributors

Datasheets & Resources

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