EPM5192JC68 vs EPM5192JC-ES Comparison

Detailed side-by-side comparison of EPM5192JC68 by Altera and EPM5192JC-ES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192JC68 EPM5192JC-ES
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $15.85 $16.45
Device Family MAX 5000 MAX 5000
Product Type EPLD (Erasable Programmable Logic Device) β€”
Logic Elements / Macrocells 192 macrocells β€”
User I/O Pins 76 [DATA_NEEDED: user I/O count for JC-ES in PLCC-84]
Number of Pins 68 β€”
Package Type PLCC-68 (J-Lead) β€”
Operating Temperature 0C to 70C (commercial, JC suffix) [DATA_NEEDED: operating temperature range for ES grade]
Supply Voltage [DATA_NEEDED: VCC] [DATA_NEEDED: VCC nominal]
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD] β€”
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX] β€”
Configuration Memory UV-Erasable EPROM EPROM (UV-erasable, one-time programmable for JC-ES)
Programmable Interconnect Programmable Logic Array + Macrocells β€”
Dedicated Inputs 12 β€”
Clock Pins 4 dedicated β€”
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Programming Tool MAX+PLUS II (legacy) β€”
Device Type β€” CPLD (EPLD)
Macrocells β€” 192
Logic Array Blocks (LABs) β€” 12
Interconnect β€” Programmable Interconnect Array (PIA)
Package β€” 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84)
Technology β€” CMOS
Programming β€” Altera MAX+PLUS II or compatible programmer
Lead-Free β€” [DATA_NEEDED: lead-free status]
MSL Level β€” [DATA_NEEDED: MSL rating]
Note β€” Datasheet source: Altera MAX 5000 family document, 52 pages

Datasheets & Resources

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