EPM5192JI vs EPM5192GC-1 Comparison
Detailed side-by-side comparison of EPM5192JI by Altera and EPM5192GC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JI | EPM5192GC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $17.85 |
| Family | MAX 5000 | MAX 5000 (Classic) |
| Device Type | EPLD (UV-erasable CMOS Programmable Logic Device) | β |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Propagation Delay (tpd) | 55 ns | β |
| Supply Voltage | 4.75 V to 5.25 V (nominal 5 V) | β |
| Technology | CMOS EPROM, UV-erasable | β |
| Package | 84-pin PLCC (windowed, J-suffix ceramic) | 100-pin Ceramic PGA (GC) |
| Operating Temperature | -40 C to +125 C (industrial, I-suffix) | [DATA_NEEDED: operating temperature grade] |
| Mounting Type | Surface Mount (PLCC socket recommended for UV erasure) | Through-Hole (PGA) |
| RoHS Status | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] | [DATA_NEEDED: RoHS status] |
| Programming Method | Altera MAX 5000 programming algorithm (device programmer) | β |
| Erasure Method | UV exposure through windowed package | β |
| Logic Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 3,750 |
| Maximum Propagation Delay (tPD) | β | 40 ns |
| Maximum Frequency (fMAX) | β | 62.5 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Process Technology | β | CMOS, UV-erasable / OTP |
| Configuration Method | β | UV-Erase / One-Time Programmable |
| Interconnect | β | Peripheral Interconnect Array (PIA) |