EPM5192LC-1 vs EPM5192LC-2 Comparison
Detailed side-by-side comparison of EPM5192LC-1 by Altera and EPM5192LC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-1 | EPM5192LC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $14.20 | $7.95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD / CPLD | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Gates | 3750 (typical usable) | β |
| Dedicated Inputs | 7 | β |
| User I/O | 64 | β |
| Number of Pins | 84 | β |
| Package Type | LDCC (Leaded Ceramic Chip Carrier), plastic windowless | β |
| Propagation Delay | 25 ns | β |
| Maximum Clock Frequency | 50 MHz | β |
| Supply Voltage | 5 V nominal (4.75 V to 5.25 V) | 5 V (typical MAX 5000 family) |
| Technology | CMOS, UV-erasable / OTP EPROM cell | β |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: commercial/industrial/military grade] |
| Programmable Memory | EPROM (one-time or UV-erasable) | β |
| Speed Grade | -1 | β |
| RoHS Status | Non-compliant (ceramic LDCC with Pb-bearing terminations) | [DATA_NEEDED: pre-RoHS legacy part β likely non-RoHS] |
| Logic Array Blocks (LABs) | β | 12 |
| User I/O Pins | β | 64 |
| Dedicated Input Pins | β | 7 |
| External Clock Inputs | β | 1 |
| Propagation Delay (tPD) | β | 45 ns (typical, -2 speed grade) |
| Maximum Internal Frequency | β | 50 MHz |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| Process Technology | β | CMOS |
| Package | β | PQCC-84 (PLCC-84, J-lead, surface mount) |
| Programming | β | Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) |