EPM5192LC-2 vs EPM5128JC-2 Comparison

Detailed side-by-side comparison of EPM5192LC-2 by Altera and EPM5128JC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192LC-2 EPM5128JC-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $7.95 $21.75
Family MAX 5000 MAX 5000
Device Type CPLD (Complex Programmable Logic Device) UV-Erasable Programmable Logic Device (PLD)
Macrocells 192 128
Logic Array Blocks (LABs) 12 β€”
User I/O Pins 64 β€”
Dedicated Input Pins 7 β€”
External Clock Inputs 1 β€”
Propagation Delay (tPD) 45 ns (typical, -2 speed grade) 45 ns (max)
Maximum Internal Frequency 50 MHz β€”
Interconnect Programmable Interconnect Array (PIA) β€”
Process Technology CMOS CMOS
Package PQCC-84 (PLCC-84, J-lead, surface mount) 68-pin CQCC (Ceramic Quad Flat Pack), windowed
Programming Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) β€”
Operating Temperature [DATA_NEEDED: commercial/industrial/military grade] [DATA_NEEDED: operating temperature range]
Supply Voltage 5 V (typical MAX 5000 family) 5 V (nominal)
RoHS Status [DATA_NEEDED: pre-RoHS legacy part β€” likely non-RoHS] Non-compliant (ceramic windowed package contains lead-bearing solder)
Dedicated Inputs β€” 7
Maximum Counter Frequency (fCNT) β€” 50 MHz
Input Setup Time (tSU) β€” 7.5 ns
Output Drive Current (IOH/IOL) β€” 12 mA DC
Mounting Type β€” Surface Mount
Program/Erase Method β€” UV (ceramic window)
Erase/Program Cycles β€” [DATA_NEEDED: minimum erase/program cycles]
Logic Family β€” TTL-compatible I/O

Datasheets & Resources

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