EPM5192LC-2 vs EPM5192LC-25 Comparison

Detailed side-by-side comparison of EPM5192LC-2 by Altera and EPM5192LC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5192LC-25

EPM5192LC-25 - MAX 5000 CPLD, 192 Macrocells, 25ns | Altera

EPM5192LC-25 Obsolete

Specification Comparison

Parameter EPM5192LC-2 EPM5192LC-25
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $7.95 $55.00
Family MAX 5000 MAX 5000
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 192 192
Logic Array Blocks (LABs) 12 β€”
User I/O Pins 64 β€”
Dedicated Input Pins 7 β€”
External Clock Inputs 1 β€”
Propagation Delay (tPD) 45 ns (typical, -2 speed grade) β€”
Maximum Internal Frequency 50 MHz β€”
Interconnect Programmable Interconnect Array (PIA) β€”
Process Technology CMOS β€”
Package PQCC-84 (PLCC-84, J-lead, surface mount) JLCC-84 (ceramic J-lead chip carrier)
Programming Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) β€”
Operating Temperature [DATA_NEEDED: commercial/industrial/military grade] 0C to +70C (commercial)
Supply Voltage 5 V (typical MAX 5000 family) 5 V (typical, MAX 5000)
RoHS Status [DATA_NEEDED: pre-RoHS legacy part β€” likely non-RoHS] Unknown (legacy ceramic package typically non-RoHS)
Product Type β€” CPLD (Complex Programmable Logic Device)
Logic Elements β€” 192 (1 macrocell β‰ˆ 1 LE in MAX 5000 architecture)
Pin-to-Pin Delay (tPD) β€” 25 ns
Speed Grade β€” -25 (25 ns)
Mounting Type β€” Surface Mount
Programmable Technology β€” UV-erasable / OTP (EPROM-based)
Programming Interface β€” JTAG / Altera programming hardware (legacy)
I/O Standard β€” TTL-compatible
Configuration Memory β€” Non-volatile EPROM (on-chip)
Manufacturer β€” Altera Corporation (now Intel PSG)

Datasheets & Resources

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