EPM5192LC-25 vs EPM5192LC1 Comparison

Detailed side-by-side comparison of EPM5192LC-25 by Altera and EPM5192LC1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192LC-25 EPM5192LC1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $55.00 $17.40
Product Type CPLD (Complex Programmable Logic Device) β€”
Family MAX 5000 MAX 5000
Macrocells 192 192
Logic Elements 192 (1 macrocell β‰ˆ 1 LE in MAX 5000 architecture) β€”
Pin-to-Pin Delay (tPD) 25 ns β€”
Speed Grade -25 (25 ns) β€”
Package JLCC-84 (ceramic J-lead chip carrier) PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier)
Mounting Type Surface Mount Surface Mount
Programmable Technology UV-erasable / OTP (EPROM-based) β€”
Programming Interface JTAG / Altera programming hardware (legacy) β€”
Operating Temperature 0C to +70C (commercial) β€”
Supply Voltage 5 V (typical, MAX 5000) β€”
I/O Standard TTL-compatible β€”
Configuration Memory Non-volatile EPROM (on-chip) β€”
Manufacturer Altera Corporation (now Intel PSG) β€”
RoHS Status Unknown (legacy ceramic package typically non-RoHS) [DATA_NEEDED: RoHS status]
Device Type β€” Complex PLD (CPLD), UV-erasable/OTP
Equivalent Gates β€” 3750
Dedicated Inputs β€” 7
User I/O Pins β€” 64
Nominal Supply Voltage (VCC) β€” 5 V
Supply Voltage Range β€” 4.75 V to 5.25 V
Maximum Clock Frequency β€” 50 MHz
Propagation Delay (tPD) β€” 40 ns
Process Technology β€” CMOS EPROM
Programming Method β€” OTP (LC plastic package); UV-erasable equivalents in JC ceramic package
Operating Temperature (Commercial 'LC') β€” 0 Β°C to 70 Β°C
JEDEC Package Code β€” S-PQCC-J84

Datasheets & Resources

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