EPM5192LC-2N vs EPM5192LC Comparison

Detailed side-by-side comparison of EPM5192LC-2N by Altera and EPM5192LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192LC-2N EPM5192LC
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $11.85 $28.40
Family MAX 5000 MAX 7000S
Macrocells 192 192
Flip-Flops 192 β€”
Logic Elements 192 macrocells (PAL/GAL-style AND-OR array) β€”
Package Type LC (ceramic J-leaded, windowed UV-erasable package family) β€”
Speed Grade -2 (tPD approximately 25 ns) β€”
Propagation Delay (typical) 25 ns β€”
Supply Voltage 5 V (typical) β€”
Programmability UV-erasable EPROM cell β€”
Mounting Type Surface Mount (LC package) Surface Mount
Operating Temperature Commercial (0C to +70C) - inferred from speed-grade -2 designation β€”
RoHS Status Compliant (per -N lead-free suffix) [DATA_NEEDED: RoHS status]
Lead-Free Yes (per -N suffix) β€”
Architecture Programmable Logic Array (PLA) with global PIA β€”
Programming Interface Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) JTAG (ByteBlaster-compatible)
Logic Array Blocks (LABs) β€” 12
User I/O Pins β€” 64
Dedicated Inputs β€” 7
Global Clock Inputs β€” 1
Propagation Delay (tPD) β€” 55 ns (typical, commercial)
Maximum Clock Frequency (fMAX) β€” 50 MHz
Supply Voltage (VCC) β€” 4.75 V to 5.25 V (nominal 5 V)
Process Technology β€” CMOS, UV-erasable/OTP EPROM configuration
Programmable Interconnect β€” Programmable Interconnect Array (PIA), fixed delay
Boundary-Scan Support β€” JTAG IEEE 1149.1
Operating Temperature (commercial) β€” 0C to +70C
Package β€” JLCC-68 (windowed ceramic, LC suffix)

Datasheets & Resources

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