EPM5192LC-2N vs EPM5192LC-25 Comparison

Detailed side-by-side comparison of EPM5192LC-2N by Altera and EPM5192LC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5192LC-2N

EPM5192LC-2N - 192-Macrocell MAX 5000 EPLD, LC-2 Speed | Altera

EPM5192LC-2N Obsolete
Altera
EPM5192LC-25

EPM5192LC-25 - MAX 5000 CPLD, 192 Macrocells, 25ns | Altera

EPM5192LC-25 Obsolete

Specification Comparison

Parameter EPM5192LC-2N EPM5192LC-25
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $11.85 $55.00
Family MAX 5000 MAX 5000
Macrocells 192 192
Flip-Flops 192 β€”
Logic Elements 192 macrocells (PAL/GAL-style AND-OR array) 192 (1 macrocell β‰ˆ 1 LE in MAX 5000 architecture)
Package Type LC (ceramic J-leaded, windowed UV-erasable package family) β€”
Speed Grade -2 (tPD approximately 25 ns) -25 (25 ns)
Propagation Delay (typical) 25 ns β€”
Supply Voltage 5 V (typical) 5 V (typical, MAX 5000)
Programmability UV-erasable EPROM cell β€”
Mounting Type Surface Mount (LC package) Surface Mount
Operating Temperature Commercial (0C to +70C) - inferred from speed-grade -2 designation 0C to +70C (commercial)
RoHS Status Compliant (per -N lead-free suffix) Unknown (legacy ceramic package typically non-RoHS)
Lead-Free Yes (per -N suffix) β€”
Architecture Programmable Logic Array (PLA) with global PIA β€”
Programming Interface Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) JTAG / Altera programming hardware (legacy)
Product Type β€” CPLD (Complex Programmable Logic Device)
Pin-to-Pin Delay (tPD) β€” 25 ns
Package β€” JLCC-84 (ceramic J-lead chip carrier)
Programmable Technology β€” UV-erasable / OTP (EPROM-based)
I/O Standard β€” TTL-compatible
Configuration Memory β€” Non-volatile EPROM (on-chip)
Manufacturer β€” Altera Corporation (now Intel PSG)

Datasheets & Resources

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