EPM5192LC vs EPM5192JC-1 Comparison
Detailed side-by-side comparison of EPM5192LC by Altera and EPM5192JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC | EPM5192JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $28.40 | $22.40 |
| Family | MAX 7000S | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | β |
| User I/O Pins | 64 | 84 |
| Dedicated Inputs | 7 | β |
| Global Clock Inputs | 1 | β |
| Propagation Delay (tPD) | 55 ns (typical, commercial) | 40 ns (speed grade -1) |
| Maximum Clock Frequency (fMAX) | 50 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | 4.75 V to 5.25 V |
| Process Technology | CMOS, UV-erasable/OTP EPROM configuration | β |
| Programmable Interconnect | Programmable Interconnect Array (PIA), fixed delay | β |
| Boundary-Scan Support | JTAG IEEE 1149.1 | β |
| Programming Interface | JTAG (ByteBlaster-compatible) | Altera MAX programming interface (parallel, pre-JTAG for this family) |
| Operating Temperature (commercial) | 0C to +70C | β |
| Package | JLCC-68 (windowed ceramic, LC suffix) | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Device Type | β | CPLD - Complex Programmable Logic Device |
| Technology | β | CMOS, UV-Erasable / OTP |
| Usable Gates | β | 3750 |
| Maximum Internal Frequency (fMAX) | β | 62.5 MHz |
| Package Type | β | 84-pin Ceramic Quad Flat Pack (CQFP), windowed |
| JEDEC Package Code | β | S-CQCC-J84 |
| Operating Temperature | β | 0 C to +70 C (commercial) |
| Configuration Memory | β | UV-EPROM (erasable under UV lamp) |
| Process | β | CMOS EPROM |
| I/O Standard | β | TTL/CMOS 5 V compatible |