EPM5192LC1 vs EPM5192LC Comparison
Detailed side-by-side comparison of EPM5192LC1 by Altera and EPM5192LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC1 | EPM5192LC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.40 | $28.40 |
| Family | MAX 5000 | MAX 7000S |
| Device Type | Complex PLD (CPLD), UV-erasable/OTP | β |
| Macrocells | 192 | 192 |
| Equivalent Gates | 3750 | β |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| Package | PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier) | JLCC-68 (windowed ceramic, LC suffix) |
| Nominal Supply Voltage (VCC) | 5 V | β |
| Supply Voltage Range | 4.75 V to 5.25 V | β |
| Maximum Clock Frequency | 50 MHz | β |
| Propagation Delay (tPD) | 40 ns | 55 ns (typical, commercial) |
| Process Technology | CMOS EPROM | CMOS, UV-erasable/OTP EPROM configuration |
| Programming Method | OTP (LC plastic package); UV-erasable equivalents in JC ceramic package | β |
| Operating Temperature (Commercial 'LC') | 0 Β°C to 70 Β°C | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| JEDEC Package Code | S-PQCC-J84 | β |
| Logic Array Blocks (LABs) | β | 12 |
| Global Clock Inputs | β | 1 |
| Maximum Clock Frequency (fMAX) | β | 50 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V (nominal 5 V) |
| Programmable Interconnect | β | Programmable Interconnect Array (PIA), fixed delay |
| Boundary-Scan Support | β | JTAG IEEE 1149.1 |
| Programming Interface | β | JTAG (ByteBlaster-compatible) |
| Operating Temperature (commercial) | β | 0C to +70C |