EPM5192LC1 vs EPM5192LC-1 Comparison
Detailed side-by-side comparison of EPM5192LC1 by Altera and EPM5192LC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC1 | EPM5192LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.40 | $14.20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Complex PLD (CPLD), UV-erasable/OTP | EPLD / CPLD |
| Macrocells | 192 | 192 |
| Equivalent Gates | 3750 | β |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | β |
| Package | PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier) | β |
| Nominal Supply Voltage (VCC) | 5 V | β |
| Supply Voltage Range | 4.75 V to 5.25 V | β |
| Maximum Clock Frequency | 50 MHz | 50 MHz |
| Propagation Delay (tPD) | 40 ns | β |
| Process Technology | CMOS EPROM | β |
| Programming Method | OTP (LC plastic package); UV-erasable equivalents in JC ceramic package | β |
| Operating Temperature (Commercial 'LC') | 0 Β°C to 70 Β°C | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic LDCC with Pb-bearing terminations) |
| JEDEC Package Code | S-PQCC-J84 | β |
| Logic Gates | β | 3750 (typical usable) |
| User I/O | β | 64 |
| Number of Pins | β | 84 |
| Package Type | β | LDCC (Leaded Ceramic Chip Carrier), plastic windowless |
| Propagation Delay | β | 25 ns |
| Supply Voltage | β | 5 V nominal (4.75 V to 5.25 V) |
| Technology | β | CMOS, UV-erasable / OTP EPROM cell |
| Operating Temperature | β | 0C to +70C (commercial) |
| Programmable Memory | β | EPROM (one-time or UV-erasable) |
| Speed Grade | β | -1 |