EPM5192LC84-2 vs EPM5192LI-2 Comparison
Detailed side-by-side comparison of EPM5192LC84-2 by Altera and EPM5192LI-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC84-2 | EPM5192LI-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $7.90 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable / OTP Complex PLD) | EPLD (Erasable/OTP Complex PLD) |
| Macrocells | 192 | 192 |
| Package | 84-pin PLCC (LC) | 84-pin PLCC (J-lead), JEDEC S-PQCC-J84 |
| Speed Grade | -2 | β |
| Supply Voltage | 5 V (TTL-compatible I/O) | 4.5 V to 5.5 V |
| Technology | CMOS, UV-erasable / OTP | CMOS, UV-erasable / OTP |
| Logic Elements | AND-OR array with macrocell flip-flops | β |
| Programming Method | Altera legacy programmer (JEDEC bitstream) | β |
| Operating Temperature | Commercial (0C to +70C) | -40 C to +85 C (industrial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-compliant (SnPb lead finish typical for this vintage) | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | Obsolete (last Altera MAX 5000 production) | β |
| JTAG Support | Vendor-specific programming interface (pre-IEEE 1532) | β |
| I/O Standard | TTL, 5V CMOS-compatible | β |
| Logic Array Blocks (LABs) | β | 12 |
| User I/O | β | 64 |
| Total Inputs | β | 72 (7 dedicated + 64 I/O) |
| Propagation Delay (tpd) | β | 55 ns (max) |
| Maximum Internal Frequency | β | 100 MHz |
| Typical Power Dissipation | β | 600 mW at 5 V / 25 C |
| Design Toolchain | β | Altera MAX+plus II |