EPM5192LC84-2 vs EPM7128ELC84-12 Comparison
Detailed side-by-side comparison of EPM5192LC84-2 by Altera and EPM7128ELC84-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192LC84-2
EPM5192LC84-2 - MAX 5000 CPLD 192 Macrocells 84-PLCC | Altera
EPM5192LC84-2 ObsoleteAltera
EPM7128ELC84-12
EPM7128ELC84-12 - 128-Macrocell MAX 7000 CPLD, 12ns, 84-PLCC
EPM7128ELC84-12 ObsoleteSpecification Comparison
| Parameter | EPM5192LC84-2 | EPM7128ELC84-12 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $10.40 |
| Family | MAX 5000 | MAX 7000 (MAX 7000E series) |
| Device Type | EPLD (UV-Erasable / OTP Complex PLD) | β |
| Macrocells | 192 | 128 |
| Package | 84-pin PLCC (LC) | 84-pin PLCC (J-Lead, QCCJ) |
| Speed Grade | -2 | β |
| Supply Voltage | 5 V (TTL-compatible I/O) | β |
| Technology | CMOS, UV-erasable / OTP | β |
| Logic Elements | AND-OR array with macrocell flip-flops | β |
| Programming Method | Altera legacy programmer (JEDEC bitstream) | β |
| Operating Temperature | Commercial (0C to +70C) | 0C to +70C (commercial) |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket compatible) |
| RoHS Status | Non-compliant (SnPb lead finish typical for this vintage) | Non-compliant (legacy 5V part, SnPb finish) |
| Lifecycle Status | Obsolete (last Altera MAX 5000 production) | β |
| JTAG Support | Vendor-specific programming interface (pre-IEEE 1532) | β |
| I/O Standard | TTL, 5V CMOS-compatible | β |
| Logic Family | β | CMOS, EEPROM-based |
| Usable Gates | β | 2,500 |
| Logic Array Blocks (LABs) | β | 8 |
| User I/Os | β | 84 |
| Propagation Delay (tpd1) | β | 12 ns |
| Internal Global Clock Frequency | β | 90.9 MHz |
| Setup Time | β | 4.5 ns |
| Supply Voltage (VCCINT / VCCIO) | β | 5 V (4.75 V to 5.25 V) |
| Programming Interface | β | JTAG (IEEE 1149.1) / ISP |
| Pin Count | β | 84 |