EPM5192LI-1 vs EPM5192JI Comparison

Detailed side-by-side comparison of EPM5192LI-1 by Altera and EPM5192JI by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192LI-1 EPM5192JI
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $16.40 $9.75
Family MAX 5000 MAX 5000
Device Type EPLD (UV-Erasable/OTP Complex PLD) EPLD (UV-erasable CMOS Programmable Logic Device)
Usable Gates 3,750 β€”
Macrocells 192 192
Maximum Toggle Frequency 40 MHz β€”
Supply Voltage 5 V 4.75 V to 5.25 V (nominal 5 V)
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns at -1 grade] β€”
User I/O Pins [DATA_NEEDED: user I/O count for JLCC variant] 64
Package Type JLCC (windowed, ceramic, UV-erasable) β€”
Process Technology CMOS EPROM, UV-erasable β€”
Speed Grade -1 β€”
Operating Temperature [DATA_NEEDED: industrial vs military range] -40 C to +125 C (industrial, I-suffix)
Pin Count [DATA_NEEDED: pin count of LI package] β€”
Mounting Type Surface Mount (JLCC with J-leads) Surface Mount (PLCC socket recommended for UV erasure)
MSL Level [DATA_NEEDED: MSL level] β€”
RoHS Status [DATA_NEEDED: RoHS status of ceramic LI variant] [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant]
Lead Free [DATA_NEEDED: lead-free] β€”
Programmable Interconnect Programmable Interconnect Array (PIA) β€”
Architecture EEPROM/EPROM-based, non-volatile, instant-on β€”
Logic Array Blocks (LABs) β€” 12
Dedicated Inputs β€” 7
Propagation Delay (tpd) β€” 55 ns
Technology β€” CMOS EPROM, UV-erasable
Package β€” 84-pin PLCC (windowed, J-suffix ceramic)
Programming Method β€” Altera MAX 5000 programming algorithm (device programmer)
Erasure Method β€” UV exposure through windowed package

Datasheets & Resources

Browse All Products Create BOM Request Quote