EPM5192LI-1 vs EPM5192LI-2 Comparison

Detailed side-by-side comparison of EPM5192LI-1 by Altera and EPM5192LI-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192LI-1 EPM5192LI-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $16.40 $7.90
Family MAX 5000 MAX 5000
Device Type EPLD (UV-Erasable/OTP Complex PLD) EPLD (Erasable/OTP Complex PLD)
Usable Gates 3,750 β€”
Macrocells 192 192
Maximum Toggle Frequency 40 MHz β€”
Supply Voltage 5 V 4.5 V to 5.5 V
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns at -1 grade] β€”
User I/O Pins [DATA_NEEDED: user I/O count for JLCC variant] β€”
Package Type JLCC (windowed, ceramic, UV-erasable) β€”
Process Technology CMOS EPROM, UV-erasable β€”
Speed Grade -1 β€”
Operating Temperature [DATA_NEEDED: industrial vs military range] -40 C to +85 C (industrial)
Pin Count [DATA_NEEDED: pin count of LI package] β€”
Mounting Type Surface Mount (JLCC with J-leads) Surface Mount
MSL Level [DATA_NEEDED: MSL level] β€”
RoHS Status [DATA_NEEDED: RoHS status of ceramic LI variant] [DATA_NEEDED: RoHS status]
Lead Free [DATA_NEEDED: lead-free] β€”
Programmable Interconnect Programmable Interconnect Array (PIA) β€”
Architecture EEPROM/EPROM-based, non-volatile, instant-on β€”
Logic Array Blocks (LABs) β€” 12
User I/O β€” 64
Total Inputs β€” 72 (7 dedicated + 64 I/O)
Propagation Delay (tpd) β€” 55 ns (max)
Maximum Internal Frequency β€” 100 MHz
Typical Power Dissipation β€” 600 mW at 5 V / 25 C
Technology β€” CMOS, UV-erasable / OTP
Package β€” 84-pin PLCC (J-lead), JEDEC S-PQCC-J84
Design Toolchain β€” Altera MAX+plus II

Datasheets & Resources

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