EPM5192LI-2 vs EPM5192LI-1 Comparison

Detailed side-by-side comparison of EPM5192LI-2 by Altera and EPM5192LI-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5192LI-2

EPM5192LI-2 - 192-Macrocell MAX 5000 PLD | Altera | 84-Pin PLCC

EPM5192LI-2 Obsolete

Specification Comparison

Parameter EPM5192LI-2 EPM5192LI-1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $7.90 $16.40
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable/OTP Complex PLD) EPLD (UV-Erasable/OTP Complex PLD)
Macrocells 192 192
Logic Array Blocks (LABs) 12 β€”
User I/O 64 β€”
Total Inputs 72 (7 dedicated + 64 I/O) β€”
Propagation Delay (tpd) 55 ns (max) β€”
Maximum Internal Frequency 100 MHz β€”
Supply Voltage 4.5 V to 5.5 V 5 V
Operating Temperature -40 C to +85 C (industrial) [DATA_NEEDED: industrial vs military range]
Typical Power Dissipation 600 mW at 5 V / 25 C β€”
Technology CMOS, UV-erasable / OTP β€”
Package 84-pin PLCC (J-lead), JEDEC S-PQCC-J84 β€”
Mounting Type Surface Mount Surface Mount (JLCC with J-leads)
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status of ceramic LI variant]
Design Toolchain Altera MAX+plus II β€”
Usable Gates β€” 3,750
Maximum Toggle Frequency β€” 40 MHz
Propagation Delay (tPD) β€” [DATA_NEEDED: tPD in ns at -1 grade]
User I/O Pins β€” [DATA_NEEDED: user I/O count for JLCC variant]
Package Type β€” JLCC (windowed, ceramic, UV-erasable)
Process Technology β€” CMOS EPROM, UV-erasable
Speed Grade β€” -1
Pin Count β€” [DATA_NEEDED: pin count of LI package]
MSL Level β€” [DATA_NEEDED: MSL level]
Lead Free β€” [DATA_NEEDED: lead-free]
Programmable Interconnect β€” Programmable Interconnect Array (PIA)
Architecture β€” EEPROM/EPROM-based, non-volatile, instant-on

Datasheets & Resources

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