EPM5192LI vs EPM5192LC84-2 Comparison
Detailed side-by-side comparison of EPM5192LI by Altera and EPM5192LC84-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LI | EPM5192LC84-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $7.10 |
| Device Family | MAX 5000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (UV-Erasable / OTP Complex PLD) |
| Macrocells | 192 | 192 |
| Usable Gates | 3,750 | β |
| Logic Array Blocks (LABs) | 12 | β |
| Maximum Operating Frequency | 40 MHz | β |
| Propagation Delay (tPD) | 55 ns | β |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | β |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable / OTP |
| Dedicated Inputs | 7 | β |
| Total Inputs | 72 | β |
| User I/O Pins | 64 | β |
| Package | 84-pin PQCC (J84) | 84-pin PLCC (LC) |
| JEDEC Package Code | S-PQCC-J84 | β |
| Operating Temperature Range | Industrial (-40C to +85C) | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | unknown | Non-compliant (SnPb lead finish typical for this vintage) |
| Family | β | MAX 5000 |
| Speed Grade | β | -2 |
| Supply Voltage | β | 5 V (TTL-compatible I/O) |
| Logic Elements | β | AND-OR array with macrocell flip-flops |
| Programming Method | β | Altera legacy programmer (JEDEC bitstream) |
| Operating Temperature | β | Commercial (0C to +70C) |
| Lifecycle Status | β | Obsolete (last Altera MAX 5000 production) |
| JTAG Support | β | Vendor-specific programming interface (pre-IEEE 1532) |
| I/O Standard | β | TTL, 5V CMOS-compatible |