EPM570F100I5N vs EPM570F100A5N Comparison
Detailed side-by-side comparison of EPM570F100I5N by Altera and EPM570F100A5N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM570F100I5N
EPM570F100I5N - 570 LEs CPLD, 100-FBGA, 5.4ns | Intel / Altera
EPM570F100I5N β ActiveAltera
EPM570F100A5N
EPM570F100A5N - MAX II CPLD, 570 LE, 100-FBGA | Intel / Altera
EPM570F100A5N β ActiveSpecification Comparison
| Parameter | EPM570F100I5N | EPM570F100A5N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.40 | $9.85 |
| Family | MAX II | MAX II |
| Device Type | CPLD (Flash-based) | β |
| Logic Elements (LEs) | 570 | β |
| Macrocells | 440 | 440 |
| Maximum User I/Os | 76 | β |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Maximum Operating Frequency | 304 MHz | 201.1 MHz |
| Propagation Delay (tPD) | 8.7 ns (max), 5.4 ns (typical) | β |
| Supply Voltage (VCCINT) | 2.375 V to 3.6 V | β |
| Typical Supply Current (ICC) | 55 mA | β |
| I/O Standards Supported | LVCMOS, LVTTL, LVDS, SSTL, HSTL (1.5/1.8/2.5/3.3 V) | β |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable | JTAG (IEEE 1149.1) / ISP |
| Global Clocks | 4 | β |
| Operating Temperature | -40C to +100C (Industrial) | 0Β°C to +85Β°C (commercial) |
| Package | 100-ball FineLine BGA (11x11 mm) | 100-ball FBGA |
| Mounting Type | Surface Mount | β |
| Process Technology | CMOS, Flash configuration cell | 0.18 Β΅m flash |
| Hot Socketing | Supported | β |
| RoHS Status | Compliant | Compliant |
| Logic Elements | β | 570 |
| Pin-to-Pin Delay (tPD) | β | 5.4 ns |
| User I/O Pins (max) | β | 76 |
| Global Clock Lines | β | 4 |
| Supply Voltage - Core | β | 3.3 V |
| Supply Voltage - I/O Banks | β | 1.5 V / 1.8 V / 2.5 V / 3.3 V |