EPM570M100C5N vs EPM570ZM100I8N Comparison
Detailed side-by-side comparison of EPM570M100C5N by Intel and EPM570ZM100I8N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM570M100C5N
EPM570M100C5N - 440 Macrocell MAX II CPLD, 100-MBGA | Intel
EPM570M100C5N β ActiveAltera
EPM570ZM100I8N
EPM570ZM100I8N - 440-Macrocell MAX II CPLD, 100-BGA | Intel / Altera
EPM570ZM100I8N β ActiveSpecification Comparison
| Parameter | EPM570M100C5N | EPM570ZM100I8N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $11.85 | $16.50 |
| Family | MAX II | β |
| Series | EPM570 | EPM570Z |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocell Count | 440 | β |
| Logic Elements | 570 | 570 |
| User I/Os | 76 | 76 |
| Number of Logic Blocks / Array Blocks | [DATA_NEEDED: number of LABs] | β |
| Number of Pins | 100 | β |
| Package | 100-MBGA (FineLine BGA, 6 x 6 mm, 0.5 mm pitch) | β |
| Maximum Frequency (fMAX) | 201.1 MHz | β |
| Pin-to-Pin Propagation Delay | 5.4 ns | β |
| Operating Supply Voltage (Core) | 2.5 V / 3.3 V | 1.8 V |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | β |
| On-Chip User Flash Memory (UFM) | 8 Kbits | β |
| Process Technology | 0.18 um, 6-layer-metal flash | β |
| Programming Interface | JTAG (IEEE 1149.1) and ISP | β |
| Operating Temperature Range | 0 C to +85 C (Commercial) | -40 C to +85 C (Industrial) |
| Mounting Type | Surface Mount (BGA) | β |
| RoHS Status | Lead-Free / Compliant | β |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | β |
| Device Family | β | MAX II |
| Number of Macrocells | β | 440 |
| Number of Logic Array Blocks (LABs) | β | 57 |
| Maximum Operating Frequency | β | 152 MHz |
| Propagation Delay (tPD) | β | 9 ns |
| Programming Technology | β | Flash, non-volatile |
| In-System Programmability (ISP) | β | Yes (JTAG) |
| Boundary Scan | β | IEEE 1149.1 (JTAG) |
| Mounting Style | β | SMD/SMT |
| Package / Case | β | 100-ball FineLine BGA (MBGA, 0.8 mm pitch) |
| Packaging | β | Tray |