EPM7096LC68-15 vs EPM7096LI68-15 Comparison

Detailed side-by-side comparison of EPM7096LC68-15 by Altera and EPM7096LI68-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7096LC68-15

EPM7096LC68-15 - MAX 7000 CPLD, 96 Macrocells, 15ns | Altera

EPM7096LC68-15 Nrnd
Intel
EPM7096LI68-15

EPM7096LI68-15 - 96-Macrocell MAX 7000 CPLD, 15ns, PLCC-68

EPM7096LI68-15 ⚠ Last Time Buy

Specification Comparison

Parameter EPM7096LC68-15 EPM7096LI68-15
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $7.20 $9.85
Family MAX 7000 MAX 7000 (second-generation MAX architecture)
Macrocells 96 96
Logic Array Blocks (LABs) 4 4
User I/O Pins 52 52
Propagation Delay (tPD) 15 ns 15 ns
Supply Voltage (VCCINT/VCCIO) 4.75 V to 5.25 V (5 V nominal) β€”
Programmable Technology EEPROM (second-generation MAX architecture) β€”
In-System Programming Yes (IEEE 1149.1 JTAG) β€”
Logic Gates (typical) 1800 gates β€”
Memory Bits Non-volatile configuration, 100 erase/program cycles per macrocell β€”
Package PLCC-68 (LC68) 68-pin PLCC (J-lead, QCCJ)
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount (J-lead)
Operating Temperature 0C to +70C (commercial) β€”
Lead-Free / RoHS Compliant per Altera product page β€”
Programming Tool Support Altera MAX+PLUS II, Quartus II; ByteBlaster / ByteBlasterMV β€”
Supply Voltage (VCCINT) β€” 5.0 V
Programmable Logic Type β€” EEPROM-based, in-system programmable (ISP)
Programming Interface β€” IEEE Std. 1149.1 JTAG
Boundary-Scan Test (BST) β€” Built-in JTAG BST circuitry
Output Option β€” Open-drain output option available
Operating Temperature Grade β€” Industrial (-40C to +85C)
Speed Grade β€” -15 (15 ns tPD)
RoHS Status β€” [DATA_NEEDED: RoHS status]
Process Technology β€” CMOS EEPROM

Datasheets & Resources

Browse All Products Create BOM Request Quote