EPM7096LC68-7 vs EPM7096LI68-15 Comparison
Detailed side-by-side comparison of EPM7096LC68-7 by Intel and EPM7096LI68-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7096LC68-7 | EPM7096LI68-15 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $9.85 |
| Family | MAX 7000 | MAX 7000 (second-generation MAX architecture) |
| Device Type | CPLD (EEPROM-based) | β |
| Macrocells | 96 | 96 |
| Logic Array Blocks (LABs) | 4 | 4 |
| User I/O Pins | 52 | 52 |
| Package | 68-pin J-Lead PLCC (LC68) | 68-pin PLCC (J-lead, QCCJ) |
| Pin-to-Pin Delay (tPD) | 7.5 ns | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | β |
| Operating Temperature | -40C to +85C (industrial, typical) | β |
| Mounting Type | Surface Mount | Surface Mount (J-lead) |
| Architecture | EEPROM, second-generation MAX | β |
| Global Clock Pins | 6 | β |
| RoHS Status | Non-compliant (legacy 5V PLCC) | [DATA_NEEDED: RoHS status] |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Propagation Delay (tPD) | β | 15 ns |
| Supply Voltage (VCCINT) | β | 5.0 V |
| Programmable Logic Type | β | EEPROM-based, in-system programmable (ISP) |
| Programming Interface | β | IEEE Std. 1149.1 JTAG |
| Boundary-Scan Test (BST) | β | Built-in JTAG BST circuitry |
| Output Option | β | Open-drain output option available |
| Operating Temperature Grade | β | Industrial (-40C to +85C) |
| Speed Grade | β | -15 (15 ns tPD) |