EPM7096LC84-10 vs EPM7096QC100-10 Comparison

Detailed side-by-side comparison of EPM7096LC84-10 by Intel and EPM7096QC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7096QC100-10

EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera

EPM7096QC100-10 Obsolete

Specification Comparison

Parameter EPM7096LC84-10 EPM7096QC100-10
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $5.10 $7.10
Family MAX 7000 MAX 7000
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 96 96
Logic Array Blocks (LABs) 4 β€”
Maximum User I/O Pins 36 β€”
Propagation Delay (tPD) 10 ns (-10 speed grade) 10 ns
Package 84-PLCC (J-Lead) 100-pin PQFP (R-PQFP-G100, 20Γ—14 mm, 0.65 mm pitch)
Process Technology EEPROM-based, 5.0 V low-power CMOS (L) β€”
Supply Voltage (VCC) 5.0 V nominal (4.75 V - 5.25 V) 4.75 V to 5.25 V
In-System Programmability Yes, via IEEE 1149.1 JTAG β€”
MultiVolt I/O 2.5 V / 3.3 V / 5.0 V mixed-voltage interface β€”
Operating Temperature Range 0C to +70C (Commercial, 'C') β€”
Configuration Memory Non-volatile EEPROM (instant-on) β€”
Programmable Interconnect PIA (Programmable Interconnect Array) β€”
Mounting Type Surface Mount (PLCC socket or SMT) Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Logic Array Blocks β€” 4
User I/O Pins β€” 76
Maximum Operating Frequency β€” 100 MHz
Technology β€” EEPROM-based CMOS
Programming Interface β€” ByteBlaster / parallel (JTAG ISP on MAX 7000S variants)
Boundary Scan β€” IEEE Std. 1149.1 (JTAG) on MAX 7000S
PCI Compliance β€” Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade)
Operating Temperature β€” 0 Β°C to +70 Β°C (commercial)

Datasheets & Resources

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