EPM7096LC84-15 vs EPM7096QC100-10 Comparison

Detailed side-by-side comparison of EPM7096LC84-15 by Altera and EPM7096QC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7096LC84-15 EPM7096QC100-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.85 $7.10
Family MAX 7000 MAX 7000
Series MAX 7000 (second-generation MAX architecture) β€”
Macro Cells 96 β€”
Logic Array Blocks (LABs) 4 β€”
Usable Gates 1,800 β€”
Pin-to-Pin Propagation Delay (tPD) 15 ns β€”
Maximum Operating Frequency 76.9 MHz 100 MHz
User I/O Pins 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) 76
Supply Voltage (VCC) 4.75 V to 5.25 V 4.75 V to 5.25 V
Programmable Type EE PLD (in-system programmable via JTAG) β€”
Programming Interface IEEE Std. 1149.1 JTAG ByteBlaster / parallel (JTAG ISP on MAX 7000S variants)
Operating Temperature 0C to +70C (commercial) 0 Β°C to +70 Β°C (commercial)
Package / Case 84-PLCC (J-Lead) β€”
Supplier Device Package 84-PLCC (29.31 x 29.31 mm) β€”
Mounting Type Surface Mount Surface Mount
Data Retention [DATA_NEEDED: data retention years] β€”
Erase/Program Endurance [DATA_NEEDED: erase/program cycle count] β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Macrocells β€” 96
Logic Array Blocks β€” 4
Propagation Delay (tPD) β€” 10 ns
Technology β€” EEPROM-based CMOS
Boundary Scan β€” IEEE Std. 1149.1 (JTAG) on MAX 7000S
PCI Compliance β€” Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade)
Package β€” 100-pin PQFP (R-PQFP-G100, 20Γ—14 mm, 0.65 mm pitch)

Datasheets & Resources

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