EPM7096QC100-10 vs EPM7096LC84-15 Comparison

Detailed side-by-side comparison of EPM7096QC100-10 by Altera and EPM7096LC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7096QC100-10 EPM7096LC84-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $7.10 $9.85
Family MAX 7000 MAX 7000
Macrocells 96 β€”
Logic Array Blocks 4 β€”
User I/O Pins 76 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split])
Propagation Delay (tPD) 10 ns β€”
Maximum Operating Frequency 100 MHz 76.9 MHz
Supply Voltage (VCC) 4.75 V to 5.25 V 4.75 V to 5.25 V
Technology EEPROM-based CMOS β€”
Programming Interface ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) IEEE Std. 1149.1 JTAG
Boundary Scan IEEE Std. 1149.1 (JTAG) on MAX 7000S β€”
PCI Compliance Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) β€”
Operating Temperature 0 Β°C to +70 Β°C (commercial) 0C to +70C (commercial)
Package 100-pin PQFP (R-PQFP-G100, 20Γ—14 mm, 0.65 mm pitch) β€”
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Series β€” MAX 7000 (second-generation MAX architecture)
Macro Cells β€” 96
Logic Array Blocks (LABs) β€” 4
Usable Gates β€” 1,800
Pin-to-Pin Propagation Delay (tPD) β€” 15 ns
Programmable Type β€” EE PLD (in-system programmable via JTAG)
Package / Case β€” 84-PLCC (J-Lead)
Supplier Device Package β€” 84-PLCC (29.31 x 29.31 mm)
Data Retention β€” [DATA_NEEDED: data retention years]
Erase/Program Endurance β€” [DATA_NEEDED: erase/program cycle count]

Datasheets & Resources

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