EPM7096QI100-15 vs EPM7096QC100-10 Comparison

Detailed side-by-side comparison of EPM7096QI100-15 by Altera and EPM7096QC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7096QI100-15 EPM7096QI100-15 - MAX 7000 CPLD 96 Macro 76 I/O 15ns | Altera

EPM7096QI100-15 - MAX 7000 CPLD 96 Macro 76 I/O 15ns | Altera

EPM7096QI100-15 ⚠ Last Time Buy

Specification Comparison

Parameter EPM7096QI100-15 EPM7096QC100-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $14.20 $7.10
Series MAX 7000 β€”
Device Type CPLD - Complex Programmable Logic Device β€”
Programmable Type EE PLD (EEPROM-based, in-system programmable) β€”
Number of Macrocells 96 β€”
Number of Logic Array Blocks (LABs) 4 β€”
Number of Usable Gates 1,800 β€”
Number of I/O Pins 76 β€”
Maximum Propagation Delay (tPD) 15 ns β€”
Supply Voltage (VCC) 4.5 V to 5.5 V 4.75 V to 5.25 V
Operating Temperature -40C to +85C (industrial, per Q-suffix) 0 Β°C to +70 Β°C (commercial)
Package / Case 100-BQFP (BQFP-100) β€”
Mounting Type Surface Mount Surface Mount
Programming Interface IEEE Std. 1149.1 JTAG (ISP) ByteBlaster / parallel (JTAG ISP on MAX 7000S variants)
Packaging Tray β€”
RoHS Status [DATA_NEEDED: RoHS compliance status not stated in verified data] [DATA_NEEDED: RoHS compliance status]
Family β€” MAX 7000
Macrocells β€” 96
Logic Array Blocks β€” 4
User I/O Pins β€” 76
Propagation Delay (tPD) β€” 10 ns
Maximum Operating Frequency β€” 100 MHz
Technology β€” EEPROM-based CMOS
Boundary Scan β€” IEEE Std. 1149.1 (JTAG) on MAX 7000S
PCI Compliance β€” Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade)
Package β€” 100-pin PQFP (R-PQFP-G100, 20Γ—14 mm, 0.65 mm pitch)

Datasheets & Resources

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